1. Field of the Invention
This invention relates to the manufacture of semiconductor devices, particularly to a method and of protecting a single trench isolation oxide from etching during epitaxial precleaning and the semiconductor structure formed thereby.
2. Discussion of the Related Art
The etching of shallow trench isolation (STI) oxides during selective epitaxial precleaning for raised source-drain applications presents a problem in thin silicon-on-insulator (SOI) and other technologies. Cleaning the Si surface prior to epitaxial growth is critical to the quality of the growth of the epitaxial layer. This is important because the device performance is strongly dependent on the eptiaxial film quality. Typically, the cleaning process involves the removal of surface contamination and also involves Si surface passivation by hydrogen termination to prevent contamination from adsorbing onto the surface prior to epitaxial growth. Pre-silicide cleaning also has strict requirements. In order to create high quality silicide without defects, it is necessary to clean and also to hydrogen passivate the Si surface. Standard cleaning and hydrogen passivation chemistries include hydrofluoric acid (HF), which, in addition to cleaning Si, causes the unwanted etching of STI. In order to clean the Si surface adequately for epitaxial growth or silicide formation, the STI is excessively etched. This is particularly problematic for thin Si SOI applications. The reason for this is that the STI thickness is directly proportional to the Si thickness and will therefore be thin for thin Si SOI. During the pre-epitaxial growth cleaning and or the pre-silicide cleaning, the entire STI may be etched. After the STI is gone, the Buried Oxide (BOX) layer begins to etch. The BOX is located directly under the active area and as the BOX etches away, it can undercut the active area. When the undercutting is excessive, the active area may peel away completely, thereby ruining the device.
Conventional STI is created by first forming a pad oxide layer on the Si substrate, then SiN is deposited and patterned by lithography and etching. The SiN is used as a hard mask to etch trenches in the Si, then a thin SiO2 liner is formed by thermal oxidation. Finally, the STI oxide is deposited and chemical mechanical polishing (CMP) used to remove silicon oxide from areas outside the shallow trench. To avoid the possibility of excessive STI etching during pre-epitaxial or pre-silicide cleaning, one solution is to deposit a protective nitride liner inside the trench after the formation of the oxide liner but before the STI fill deposition. There are two main disadvantages to this method. The first problem is that the upper part of the nitride liner will get etched during removal of the pad nitride layer, resulting in a divot adjacent to the active region. The divot is subsequently filled with polysilicon during gate polysilicon deposition and the polysilicon in the divot can cause unwanted electrical connections between adjacent gates and also create a so-called xe2x80x9cwraparoundxe2x80x9d gate. The wraparound gate results in a lowering of the threshold voltage, which causes premature activation of the transistors. The second problem is that a nitride layer cannot protect any STI oxide on top of it. All of the STI oxide above it can be etched away, thereby compromising planarity. What is needed is a method of protecting the shallow trench isolation (STI) during oxide etching processes.
Disclosed is a method of protecting a semiconductor shallow trench isolation (STI) oxide from etching, the method comprising lowering, if necessary, the upper surface of said STI oxide to a level below that of adjacent silicon active areas, depositing a nitride liner upon said STI oxide and adjacent silicon active areas in a manner effective in defining a depression above said STI oxide, filling said depression with a protective film, removing said nitride layer from said adjacent active areas.
In another aspect of the invention said deposition of a nitride liner is effected with a chemical vapor deposition.
In another aspect of the invention said chemical vapor deposition is one selected from a low pressure chemical vapor deposition, a rapid thermal chemical vapor deposition, a plasma-enhanced chemical vapor deposition, or a high-density plasma chemical vapor deposition.
In another aspect of the invention said chemical vapor deposition further comprises reacting a silane derivative with ammonia.
In another aspect of the invention said protective film is an organic polymer.
In another aspect of the invention said organic polymer is a planarizing polymer.
In another aspect of the invention said planarizing protective polymer is an anti-reflective coating polymer.
In another aspect of the invention said anti-reflective coating polymer is one selected from mixtures of acrylates and methacrylates, mixtures of polyurea and polysulfone polymers, and copolymers of benzophenone and bisphenol-A.
In another aspect of the invention said planarizing protective polymer is a photo-resist polymer.
In another aspect of the invention, said photo-resist polymer is a novolak resin.
In another aspect of the invention said protective film is a spin-on oxide.
In another aspect of the invention said protective film is conformal and is planarized by chemical mechanical polishing.
In another aspect of the invention said filling of said depression with protective film comprises depositing a layer of said protective film over said nitride layer, recessing said protective film such that said protective film remains only in said depression.
In another aspect of the invention said protective film is an organic polymer and said recessing is effected with a plasma etch.
In another aspect of the invention said protective film is removed from said depression.
In another aspect of the invention, said protective film is removed from said depression with a reactive ion etch.
Disclosed is a method of protecting a semiconductor shallow trench isolation (STI) oxide from etching, the method comprising lowering, if necessary, the upper surface of said STI oxide to a level below that of adjacent silicon active areas, executing a chemical vapor deposition to deposit a conformal nitride liner upon said STI oxide and adjacent silicon active areas in a manner effective in defining a depression above said STI oxide, covering said nitride liner with a protective film comprising an organic polymer, recessing said protective film with a plasma etch, such that said protective film remains only in said depression, removing said nitride layer from said adjacent active areas with a reactive ion etch, removing said protective film from said depression with a plasma etch.
Disclosed is a semiconductor structure, comprising a plurality of active areas separated by one or more shallow trench isolations wherein only said shallow trench isolations are covered by a protective layer of silicon nitride.
Disclosed is a semiconductor structure comprising a plurality of active areas separated by one or more shallow trench isolations, said active areas and shallow trench isolations covered by a layer of silicon nitride, wherein said layer of silicon nitride comprises depressions over said shallow trench isolations, a protective film disposed in said depressions.
Disclosed is a method of protecting a semiconductor shallow trench isolation (STI) oxide from etching, the method comprising providing means for lowering, if necessary, the upper surface of said STI oxide to a level below that of adjacent silicon active areas, providing means for depositing a nitride liner upon said STI oxide and adjacent silicon active areas in a manner effective in defining a depression above said STI oxide, providing means for filling said depression with a protective film, providing means for removing said nitride layer from said adjacent active areas.